China's Open Source Says 'Ascend Only' in the Fine Print — The Localization Paradox

Software released as open source, with this sentence sitting in its license. The licensee "shall not make any use of the Software to develop or distribute software for use in systems with processors other than Ascend processors."

The license is attached to one repository inside CANN, Huawei's AI software stack. Its name: CANN Open Software License Agreement Version 1.0. Neither Apache nor MIT. Huawei wrote this one itself and attached it. You can read the source. You can fix it. What the license blocks is walking that code over to an Nvidia or an AMD chip.

That sentence is Part 3's question in miniature. China is picking materials U.S. sanctions can't reach and stacking its own platform on them: RISC-V, the royalty-free open instruction set, and software whose source has been published. If what gets built that way is one more stack nobody can leave, what exactly has been localized?

This is Part 3 of the PRISM series "The Semiconductor Sovereignty War." Part 1 found Nvidia's defensive line outside the silicon, in roughly 20 years of accumulated CUDA software. Part 2 surveyed the open-standard counterattack on that moat and left one thread hanging: the party that embraced open standards most urgently was a state. Part 3 is that thread.

The paradox runs two layers deep. Openness was picked to break lock-in, and what openness is building is one more lock-in. Sovereignty is the banner, and the two weakest links still hang outside the country. Training compute is tied to Nvidia, manufacturing to foundry capacity.

A sentence in the plan, a line item missing from the purchase order

On August 12, China's Central Government Procurement Center, the bulk buyer for central state organs and roughly the counterpart of the U.S. GSA schedule, published the winners of a consolidated desktop PC tender. 4,496 machines. Six domestic CPU platforms took all of them: Hygon 2,059, Kunpeng 1,053, Loongson 494, Zhaoxin 472, Phytium 303, Sunway 115 (Chinese media citing the procurement center's notice, August 13, 2026). RISC-V appears in none of the six.

A month later, on September 15, the Ministry of Industry and Information Technology (MIIT) and the National Development and Reform Commission (NDRC), China's top industrial planner, distributed the 15th Five-Year Plan for the Electronic Information Manufacturing Industry. Document 工信部联规〔2026〕216号, dated September 10. Xinhua, the state news agency, quoted the plan, and RISC-V sits inside the sentence it quoted: the plan calls for advancing "research, development and industrialization of the fifth-generation reduced instruction set (RISC-V)" (Xinhua, September 16, 2026). The notice MIIT posted on its own site carries no attachment with the plan's text, and the ministry's official explainer runs through four priority tasks without naming RISC-V once.

The distance between those two documents is where Chinese RISC-V sits today. The sentence made it into the national plan. The line item didn't make it onto the central government's purchase order. One qualifier: this tender covers desktop PCs bought in bulk. Server and AI accelerator procurement falls outside it.

The gap gets pointed out inside China too. A column called Xinghai Qingbaoju, carried on Sina Finance, called it a "glass ceiling" in April (April 7, 2026). Tencent and ByteDance have put their names on the RISC-V camp, the same column noted, and RISC-V's share of either company's core hardware buying stays negligible.

One widely cited document needs handling first. A line has spread, in Asia and in the West, that "eight Chinese ministries jointly issued a national RISC-V development guideline in March 2025." The original report is Reuters. On March 4, 2025, Reuters reported that eight government bodies, the Cyberspace Administration of China, MIIT, the Ministry of Science and Technology and the China National Intellectual Property Administration among them, were preparing a guideline together. The wording was "being drafted," with a caveat that it could come as soon as that month, though the final date could change. A year later, one Chinese finance column rewrote that as "jointly released." It's the same column that diagnosed the glass ceiling, and later citations treated it as fact. As of September 2026, no document number, no release date and no published text for this guideline can be found through Chinese government channels. Set that against the September 15 plan, which arrived with a number on it.

Washington's picture is empty in a similar way. Calls to put RISC-V on the export-control list have recurred since 18 members of Congress wrote to the Commerce Secretary in November 2023. This August, retired colonel Mike McCalister made the same case to House Foreign Affairs Chairman Brian Mast in a signed column in Florida Politics. The piece ran as a guest op-ed and an advocacy push, and no bill followed from it. The House Foreign Affairs Committee did advance a bill on AI chip exports to China in January 2026, and whether that bill takes explicit aim at RISC-V is unconfirmed. Three years of demands have piled up and no rule has come out. The premise Part 2 set, RISC-V sitting outside export-control range, still holds.

One server CPU, one roadmap

At the chip layer, RISC-V's face in China is Alibaba.

XuanTie C950, unveiled on March 24 at an Alibaba DAMO Academy event, is a server-class RISC-V CPU. The company's specs: eight-instruction decode, a 16-stage pipeline, an out-of-order window above 1,000 instructions, up to 3.2GHz, and a single-core SPECint2006 score over 70 (TrendForce and EE Times, March–April 2026). Alibaba said the chip had been verified for 5-nanometer production technology. It didn't say which foundry makes it. That comes back later.

Keep one distinction. Zhenwu M890, which Alibaba calls an AI processor, is a separate product. At its August 20 earnings release the company said M890 had been adopted through Alibaba Cloud by more than 650 external customers across 20-plus industries. In the same release, AI cloud and compute services revenue hit $7.1 billion, up 45% year-over-year, and quarterly capital spending ran to nearly $10 billion, up 75% (Alibaba earnings materials, August 20, 2026). Neither RISC-V nor XuanTie appears in that document.

Alibaba's Yunqi Conference ran in Hangzhou from September 22 to 24. XuanTie didn't take the keynote stage.

What Alibaba Group CEO Wu Yongming unveiled is an AI accelerator, Zhenwu V900. The company says a single chip delivers three times the performance of its predecessor M890, with 216GB of memory and 1,200GB/s of chip-to-chip interconnect, and it put volume production at the first quarter of 2027 (21st Century Business Herald and Sina Finance, September 22, 2026). No third-party benchmark exists yet. These are company claims.

A server CPU roadmap came out for the first time as well: Yitian 720 and 730 in the third quarter of 2027, with 730 the first part to carry a CPU microarchitecture designed entirely in-house by T-Head, Alibaba's chip unit (Sina Finance, September 22, 2026). Keep those two apart. What the reports describe is a microarchitecture, and they say nothing about the instruction set. Yitian 710 is an Arm-family part, and this announcement carries no ISA designation. An in-house microarchitecture is a different thing from an in-house instruction set.

And something's absent. Neither XuanTie nor RISC-V appears in the keynote coverage from Sina Finance, 21st Century Business Herald and other major outlets. The company had unveiled a server-class RISC-V CPU in March, and the national plan had put RISC-V in writing a week earlier. At Alibaba's biggest event of the year, the weight landed on the accelerator (Zhenwu V900) and the server CPU (Yitian).

Here's the misreading to cut off early. RISC-V entering a Chinese national plan doesn't mean Chinese AI accelerators run on RISC-V. The compute cores in Huawei's Ascend are Da Vinci, an architecture Huawei designed itself: a cube unit for matrix math, a vector unit, a scalar unit (Huawei presentation materials and academic literature). Cambricon uses an instruction set of its own, MLUarch. Across two consecutive years of Connect press releases, Huawei has never named RISC-V as Ascend's architecture.

Split the stack into layers and the materials come into view. The AI accelerator's compute cores are Huawei's own architecture. The server host CPU layer holds Huawei's Kunpeng (Arm family), Loongson and Phytium, with Alibaba's XuanTie beside them. That's where RISC-V stands. The chip-to-chip interconnect is UnifiedBus, a Huawei specification, and the company published its spec as an open standard last year. The software stack is CANN. So "materials sanctions can't reach" covers two different layers: an instruction set, and software. Blur them into one and the picture comes out wrong.

The accelerator roadmap belongs to Huawei. At Huawei Connect 2026 in Shanghai on September 17, Vice Chairman and Rotating Chairman David Wang announced Ascend 960DT for the first quarter of 2027 and 960PR for the third, which by the company's account pulls each in by three quarters and one quarter. On the roadmap Rotating Chairman Eric Xu presented at Connect 2025, Ascend 960 was a single product slated for the fourth quarter of 2027. Q4 2027 to Q1 2027 is exactly three quarters; to Q3 2027, one. The acceleration the company described checks out against its own roadmap from last year.

970 arrived without a quarter this time, so there's nothing to compare it against. The products confirmed as pulled forward are 960DT and 960PR.

One reversal in the sequence stands out. In Huawei's naming, PR and DT are derivatives sharing a die, and last year the company described 950DT as a part aimed at "training and decoding." In the 950 generation, the inference-oriented PR came in the first quarter of 2026 and the training-oriented DT in the fourth. In the 960 generation, DT comes first, and DT is also the part pulled in by three quarters. If training is the weak link in China's stack, Huawei has rearranged its launch order to aim at that link. That last part is interpretation. The company gave no reason for the change in its announcement.

The counter-reading came out of the same venue. China tech analyst Rui Ma pointed out that the chips themselves are arriving much earlier while the SuperPoD announced this time is far smaller than what was originally laid out (The Next Web, September 18, 2026). The Atlas 960 SuperPoD Huawei described last year was a 15,488-chip system. The Atlas 960E SuperPoD announced this time scales up to 4,096 NPUs, 8 exaflops of FP8 and up to 1 petabyte of HBM (company specs). Two similar names, nearly four times apart in scale. A gap remains per chip too: the same outlet put 960DT's up-to-288GB of memory and 4 petaflops of FP4 at half of Nvidia's B300 on FP8 and a third on FP4.

The boundary of openness

Now the software. This layer is Part 3's center.

CANN is the software stack that runs AI computation on Ascend chips, doing for Ascend what CUDA does for Nvidia GPUs. At Connect 2025 on September 18 last year, Rotating Chairman Eric Xu announced the stack would be opened. The wording: for the compiler and virtual instruction set, Huawei would "open interfaces," and it would "fully open-source other software." The deadline was December 31, 2025. The Mind series of development tools and Pangu, Huawei's own foundation model, were tied to the same date.

The compiler is the first thing to look at there. Part 1 concluded that the substance of Nvidia's moat is layer on layer of libraries and compilers with a developer base resting on top. The part Huawei opened only at the interface is exactly that layer. The compiler implementation itself was never inside the scope of the opening.

A year later at Connect 2026, the company said CANN had "moved to sustained, community-driven open-source development," with numbers attached: external developers make up 61% of all CANN developers, and monthly active developers exceed 5,200. All of it is Huawei's own tally, and none of it has been verified independently from outside. A good share of the repositories block bot access, so this reporting couldn't count contributors directly either. What's confirmed stops here: the CANN repositories are publicly readable as of September 2026.

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The temptation is to line those up against CUDA, and the units don't match. The roughly 6 million CUDA developers Part 1 cited is a cumulative figure built over nearly two decades. Huawei's 5,200 is monthly active developers. Side by side, the two numbers produce a misreading.

Then there's the license.

We opened and read the license file in cann-hccl, the collective communication library among CANN's components. The document is titled "CANN Open Software License Agreement Version 1.0." Three clauses stand out. A user may "develop software solely for use with Ascend processors" and "shall not make any use of the Software to develop or distribute software for use in systems with processors other than Ascend processors." The license is "royalty-free, non-transferable, non-sublicensable, and revocable." And Huawei may terminate the agreement if a user initiates legal proceedings alleging that the software infringes their intellectual property.

The license doesn't appear on the Open Source Initiative's list of approved licenses. Nor is every Huawei repository bound by one license. AscendNPU-IR, the repository handling the NPU's intermediate representation, uses Apache 2.0. Terms differ from repository to repository.

Lay Part 1's definition of the moat over this and the picture sharpens. Part 1 defined Nvidia's defensive line as porting cost: the arithmetic where moving to another chip costs more than the new chip gains you. CANN shows you the source, and a sentence in the license blocks taking that source to another chip. Visible code leaves the porting cost standing.

Governance sits somewhere different too. As Part 2 showed, RISC-V International, which stewards RISC-V, moved its headquarters to Switzerland in 2020, stepping onto neutral ground so that no single government could control an open collaboration. CANN has no equivalent transfer. Licensing authority stays with the company, and no handoff to the Linux Foundation or the Apache Software Foundation has been announced. Open "standard" and open "source" share a word and differ in the character of their governance.

The view from the other side is real and worth stating plainly. CANN is more auditable than CUDA, whose source is closed outright. CANN can be read, its bugs found and fixed, its behavior checked. For Chinese institutions and developers who've depended on a foreign black box, that's a concrete sovereignty gain, and if external developers really are 61% by the company's count, a community is forming. "Fake open source" overshoots as a label. What's accurate is narrower: the scope of the opening stops at the hardware boundary.

Defaults deserve a paragraph. At Connect 2026 Huawei said Ascend is "the first official Chinese compute platform on PyTorch's website." On PyTorch's official site, the compute platforms selectable in the front-page installer are three CUDA versions, ROCm and CPU. Ascend isn't there. The site points anyone who "could not find the right platform for your hardware" to a separate Additional Platforms page, which lists platforms "provided by our partners and community members" and carries its own column marking the support channel. Nothing here makes the company's claim false. torch_npu, the PyTorch backend for Ascend, exists, and its repository is active. The default slot on the install screen still belongs to CUDA. It's the scene that shows where the moat Part 1 described actually lives.

The company said Ascend supports more than 90 third-party open-source projects, PyTorch, Triton, vLLM and veRL among them. The list hasn't been published and there's no way to check it. Triton's presence is worth flagging. Part 2 introduced Triton as the most fundamental weapon of vendor neutrality. That neutral layer is being absorbed into the Chinese stack.

Answer this section's question and it comes out like this. Opening CANN increased auditability. It didn't increase portability. The visibility of the source code changed, and the freedom to move to another chip stayed tied down. The lock-in mechanism sits where CUDA's sits. What changed is the nationality of the company holding it.

Inference moved, training stayed

Move up to the model layer and the boundary sharpens.

In April, reports said DeepSeek V4, a mixture-of-experts model with 1.6 trillion parameters, had completed inference validation on Ascend 950PR (Tom's Hardware and TrendForce, April 2026). Five months later, Bloomberg reported exclusively on September 4 that DeepSeek had drawn up plans to install more than 160,000 Ascend 950DT chips at a new data center in Inner Mongolia. The same report specified that these chips are for inference only and that training continues on Nvidia GPUs. Second-hand citations are everywhere; the original report is Bloomberg's alone. And 950DT is a fourth-quarter product on Huawei's roadmap. The company has never announced mass production or shipment of it, and the Connect 2026 press materials don't mention the 950 series at all. Which makes this a deployment plan for a chip that hasn't arrived.

On post-training, a paper landed in July: arXiv 2607.20145, titled "SLAI T-Rex: Full-Parameter Post-training of the DeepSeek-V4 Family on Ascend SuperPOD." It carries 65 authors, and the institutional author is the AI Training Platform Team at the Shenzhen Loop Area Institute. Huawei doesn't appear in the paper's author listing, and its participation is confirmed only through press reports. The system used is a CloudMatrix384 SuperPoD running Ascend 910C, and the total chip count isn't written in the paper. The "at least 1,000" figure often quoted alongside it doesn't come from the paper. It came out of Shenzhen municipal government material.

What the paper reports is hardware utilization pushed from 11.67% to 34.22%. That measure is model FLOPs utilization, or MFU, the share of a machine's theoretical peak compute a run actually puts to work. The team wrote it up as "a 2.93x improvement over the open-source baseline recipe." Read the comparison carefully. The baseline for that 2.93x is the team's own unoptimized configuration, and no comparison against Nvidia appears anywhere. Multiply 11.67 by 2.93 and you get 34.19. It's the same structure as Part 2's account of AMD describing ROCm 7.0's gains as "up to 4x," where the baseline was the previous version, ROCm 6. Second trap of its kind this series has run into.

Above all, the paper covers post-training only, the stage that takes an already-trained model and refines it further. The paper states of itself that it doesn't establish which hardware trained DeepSeek-V4 in the first place. Tsinghua University professor Liu Zhiyuan publicly noted that DeepSeek appears to have adapted only part of the V4 training process to domestic chips, and that the model may still have been trained mainly on Nvidia hardware (cited by MIT Technology Review). Tom's Hardware took issue with the absence of benchmarks behind the original claim.

Building an AI model splits into three boxes. Pre-training learns parameters from the ground up. Post-training fine-tunes and aligns a model already trained. Inference runs the finished model to produce answers. The compute required is overwhelmingly concentrated in the first. The stretch where Ascend has results is the latter two. Evidence that pre-training has been done on Ascend has never been published.

Unit counts and compute

At Connect 2026 Huawei said it had deployed more than 1,000 Atlas 900 A3 SuperPoDs, without disclosing customers, regions or dates. There's no third-party confirmation. On how much Huawei actually builds, one estimate exists outside the company's own announcements.

Epoch AI, an independent AI research institute, published an analysis on September 4 titled "Will Huawei catch up to Nvidia by 2030?" By its estimate, Huawei produces 1.5 million Ascend-family chips in 2026 against Nvidia's 5.9 million. Counted in units, Huawei comes to about a quarter of Nvidia. In the same estimate, H100-equivalent compute comes to 880,000 for Huawei and 23 million for Nvidia. As a share, that lands under 4%.

Same year, same two companies: change the unit and the conclusion flips. Count the units and it looks like a chase. Count the compute and the gap stays where it was. These are estimates and can't be stated as fact, though the direction doesn't conflict with other analysis. The Council on Foreign Relations also puts Huawei's 2026 share near 4%.

Epoch AI identified three constraints. HBM memory is the binding constraint. SMIC is stuck at 5 to 7 nanometers with no access to Taiwan's leading-edge processes. And per-chip performance trails Nvidia by three to four years. The report's conclusion reads: "Huawei's published roadmap is ambitious but insufficient given Nvidia's own progress on per-chip performance." And export controls "constrain its most important scaling levers, making it unlikely to catch up with Nvidia."

That answers an argument already running in the English-language press. On one side is Jensen Huang's backfire thesis, that controls accelerated Chinese localization instead. On the other is Congress's position, that controls need tightening. It's the battlefield this series took up in Part 4. Epoch AI's estimate puts its weight on the side that says controls are working.

One more thing for the record. Every Huawei performance figure in this article is a number the company published itself. For the latest Ascend 950 and 960 families, no submissions to public benchmarks such as MLPerf can be confirmed. The older 910 has a submission history in MLPerf training around 2020, and Huawei's storage products are still submitted today. The blank is specific to the latest AI accelerators. Huawei wasn't on the MLPerf training submitter list last November or this June either.

Utilization 93.7%

The second weak link is manufacturing.

SMIC filed second-quarter results on August 13. Reports citing the filing put revenue at $3.006 billion, up 20.0% from the previous quarter and 36.1% year-over-year. Three numbers are worth watching: utilization of 93.7%, monthly capacity of 1,096,500 wafers in 8-inch equivalent, and wafer shipments of 2,869,000.

Set them against the prior quarter and a picture emerges. Utilization climbed from 93.1%, and the company guided to holding the mid-90s through the third quarter. Capacity grew 1.7% from 1,078,300 wafers. Shipments grew 14.4%. Average wafer prices rose 5.7% quarter-over-quarter, and gross margin jumped from 20.1% to 25.3%. That's the combination you get when capacity expansion can't keep pace with demand, and it happened after roughly $3.4 billion of capital spending in the first half.

Break revenue down by application and the distance from the leading edge shows. In the second quarter, consumer electronics took 44.2% of revenue, smartphones 16.9%, industrial and automotive 16.5%, and computers and tablets 15.6%. By region, 90.2% came from inside China. In this set of results SMIC didn't mention 5nm, or any advanced node, even once. The same absence shows up in both the English and the Chinese summaries. What the company named as AI-related demand was power management chips and interface chips.

Alibaba's C950 ties off here. Alibaba said the chip had been verified on a 5-nanometer process and didn't disclose the foundry. Nikkei Asia reported on March 26, citing multiple sources, that TSMC would make it once it progressed to the production stage. That's a future-tense sentence, and at that point C950 was pre-production. Neither Alibaba nor TSMC has ever confirmed or denied it. What's clear is that 5nm can't be run in mainland China. TSMC's Nanjing fab is limited to mature nodes at 16nm and above, and EUV lithography, the Dutch-built machines the leading edge requires, can't be shipped into China. The U.S. Commerce Department's Bureau of Industry and Security issued a rule in January last year restricting Chinese design houses from receiving advanced-node chips from abroad. Whether C950 falls under that rule's performance threshold takes a separate judgment. What can be said here stops at this: the Taiwan-fab route isn't self-evident.

Memory sits in the same spot. HBM is the first constraint Epoch AI named for Huawei. At Connect 2025 last year Huawei unveiled HBM of its own, HiBL 1.0 and HiZQ 2.0, and neither name appears in this year's Connect 2026 press materials. That no progress was updated is itself information. SemiAnalysis, a semiconductor research firm, also picked HBM over wafer capacity as China's bottleneck in an analysis last September. That this is a diagnosis from a year ago has to be factored in.

One announcement, four readings

How this stack looks depends on which language you read it in.

Taiwan splits internally. Economic Daily News covered Ascend 960's early arrival in a "throwing down the gauntlet to Nvidia" frame and wrote that progress is running ahead of expectations. Around the same time Newtalk headlined "competing on compute by stacking chips." The implication is brute volume, pointing the same direction as Rui Ma and The Next Web.

Mainland outlets read the same facts at the opposite value. Sina headlined that doubling single-card performance is merely the foundation and that Huawei Ascend 960's breakthrough lies in cluster interconnect. The spot Western analysis calls a per-chip performance gap, the mainland reads as cluster being the whole point. Same fact, different valuation.

The coordinate of those who sell the standard differs again. Taiwan's Andes Technology holds more than 30% of the global RISC-V IP market, licensing CPU cores the way Arm does. Its largest source of revenue in 2025 was the United States at 37%, with Taiwan at 36% behind it. The company has called China a market with intense price competition and said it moved its weight toward AI, industrial and automotive applications (earnings call, March 18, 2026). Meta's MTIA inference chip, covered in Part 2, adopted this company's cores and went into volume production. On the same open standard, Beijing talks sovereignty and Taipei talks unit price.

Japan looks at it through equipment. Tokyo Electron's China revenue share was tallied at 34.1% for the fiscal year ended March 2026 and 26.8% in the fourth quarter (based on earnings-briefing materials as relayed by Japanese media). The reason cited for the decline was faster growth in investment for leading-edge processes. Japanese equipment makers hold a double position: beneficiary of Chinese localization, and obliged to cut China exposure at the same time.

For readers in Washington and Brussels, those positions arrive from the other side of the same line. The tools, the lithography and the memory that China's stack still needs come from companies whose governments are party to the controls.

Korea has a more direct layer. Huawei Korea CEO Balian Wang said at a Seoul press briefing last December that the company would bring AI computing cards and AI data center solutions to Korea in 2026 and introduce Ascend 950, supplying cluster configurations rather than selling chips individually. Korean outlets largely received this with the word "hope." TrendForce reported in July, citing Korean media, that Huawei Korea was looking to launch the Ascend 950 family and the Atlas 950 SuperPoD in Korea in the fourth quarter, with distribution pursued through a local partner. The same report named local sensitivity toward Chinese technology and heat-driven power consumption as obstacles.

There's a design-side coordinate as well. RVX, a RISC-V design platform from ETRI, Korea's state-funded electronics and telecommunications research institute, is a case of a royalty-free standard lowering the entry barrier for domestic fabless firms. The prevailing industry assessment is that its commercial viability still falls short of Arm.

One more gate. At the center of the HBM market Epoch AI named as Huawei's constraint stand Samsung Electronics and SK hynix. In this configuration, Korea's memory industry is the decisive gate for China's AI expansion, the side subject to China-related regulation, and the substitution target that Huawei's in-house HBM and CXMT's capacity expansion are aiming at. All three positions hold at once.

The coordinates that remain

Part 3 leaves two facts behind. China has built its own stack out of materials sanctions can't reach, from CPUs and accelerators through software and models. And two layers of that stack still hang outside: compute that can carry pre-training, and manufacturing capacity that can run leading-edge processes.

RISC-V made it into China's plan as a sentence. It hasn't made it onto the central government's desktop purchase order. The distance between those two documents is localization's current coordinate. RISC-V Summit China opens in Shenzhen on October 18, with David Patterson, who designed RISC-V, and Andrea Gallo, CEO of RISC-V International, on the keynote list. An organization that moved its headquarters to Switzerland to secure neutrality takes the stage in a city of the country that wrote that standard into its own five-year plan.

The series' fourth installment is already out. After Part 1's CUDA moat and Part 2's open-standard counterattack, and with Part 3's Chinese stack, the place to read next is Part 4, on export controls. It covers the phase where regulation moves market share directly.