Nvidia Put a Billion RISC-V Cores in Its Own Chips. Can the Open Standard Route Around CUDA?

Nvidia Put a Billion RISC-V Cores in Its Own Chips. Can the Open Standard Route Around CUDA?

Nvidia owns the moat. It's also one of the biggest users of the standard aimed at it.

In 2024 alone, Nvidia shipped roughly a billion RISC-V cores inside its own GPUs, CPUs, and SoCs — the royalty-free, open instruction set architecture that anyone can use without a license (RISC-V International blog, 2024). Ten to forty of them ride on a single chip, and the GSP control processor that manages the GPU has moved over to 64-bit RISC-V. Then, in July 2025, the company went a step further, announcing it would run its CUDA platform on a RISC-V host CPU (RISC-V International and Tom's Hardware, July 2025). The feature hasn't shipped. It's still in development, with no public timeline. But the direction is unmistakable: the owner of the CUDA moat is among the heaviest users of the open standard being sharpened against it.

This is Part 2 of PRISM's Semiconductor Sovereignty series. Part 1 landed on a single conclusion: Nvidia's real line of defense is the CUDA software ecosystem it has spent nearly 20 years building. That's why its share hasn't budged even as the silicon race turned into a dead heat. So where does the counterattack come from? If a faster engine can't route around the road, what happens when you open up the road's blueprint itself? That's the question for Part 2.

The weapon is zero royalties

To see what makes RISC-V different, start with the gatekeeping in older instruction sets. An ISA is the spec software uses to talk to a chip, the road rules of the silicon. x86 is effectively closed to anyone outside Intel and AMD; new entrants can't get a license at all. Arm opens the door but charges steep licensing fees plus a per-chip royalty. RISC-V works on a different principle. Born at UC Berkeley in 2010, it carries no royalties and no license fees. Follow the spec, and anyone can use it, modify it, and extend it.

That openness translates into three freedoms: zero licensing cost, the freedom to add custom extensions, and supply sovereignty, the ability to pick your own fab, OS, and IP. Meta captured the appeal when it explained why it chose RISC-V for its MTIA accelerator: no royalties owed to a third party, and the freedom to customize the instruction set at whatever pace it needs (Meta AI blog and Tom's Hardware, 2024-2025).

Even the governance sits where it does for geopolitical reasons. RISC-V International, the body that stewards the standard, began as a Delaware nonprofit. In December 2018 it decided to move its headquarters to Switzerland, completing the move by March 2020 (Reuters and The Register, 2019). Amid the US-China trade war, members worried about "potential geopolitical disruption," and the group relocated to neutral ground so no single government could control open collaboration (then-CEO Calista Redmond, quoted by Reuters). That decision feeds directly into China's RISC-V strategy, which Part 3 will take up.

The standard's evolution is aimed squarely at AI, too. RVV 1.0, the vector extension for parallel numeric work, was ratified and frozen in November 2021 (RISC-V International). Then on October 21, 2024, the RVA23 profile for application processors was ratified, making vector support mandatory and folding in AI data types like FP8 and BF16 (RISC-V International blog, 2024). It's widely read as the turning point that finally tamed the fragmentation that plagued early RISC-V.

The silicon is already on sale

A standard that lives only on paper isn't a counterattack. The hardware has to sell. And it's selling.

The most visible face is Tenstorrent, led by Jim Keller, the engineer behind AMD's Zen, Apple's A-series, and Tesla's self-driving chip. The company's latest card, the Blackhole p150a, sells for $1,399. It packs 768 RISC-V processors across 120 Tensix compute cores, with larger cores capable of running an OS, so it operates standalone without a separate x86 host CPU (Tenstorrent official specs, 2025). By the manufacturer's spec, it hits 664 teraflops of BLOCKFP8 compute. The lower-cost entry point, the Wormhole n300d, runs $1,449.

The software strategy is as striking as the numbers. Tenstorrent open-sourced its entire stack under Apache 2.0: the TT-Metalium driver layer, the TT-NN neural-network library, and the TT-Forge model compiler, the open-source counterparts to CUDA's layers (EE Times, 2025). Keller has boiled the strategy down to a line that became an EE Times headline: "Whatever Nvidia does, we'll do the opposite." Late in 2025, the company raised roughly $800 million at a valuation of about $3.2 billion (EE Times and others).

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A caveat rides along with all this. Tenstorrent's performance numbers are manufacturer specs, and they don't guarantee real-world parity with CUDA's libraries on speed or maturity. Third-party benchmarks are still thin. Even the vendor's own specs can shift: the company cut the Blackhole p150's Tensix cores from 140 to 120 via a firmware update, warning existing users to expect a 1-2% performance drop (Tom's Hardware, 2025). Reason enough not to take catalog figures at face value.

Tenstorrent isn't alone, though the players sit on different layers. RISC-V's push into AI splits three ways: standalone accelerators, data-center server CPUs, and hyperscalers' in-house silicon. Tenstorrent holds the standalone-accelerator slot. Alongside it, SiFive supplies AI-focused IP like the X280, which pairs the RVV 1.0 vector extension with a VCIX interface for bolting on external accelerators, and rolled out a second-generation lineup in September 2025 (SiFive and CNX Software, 2025). The server-CPU slot goes to Ventana's Veyron V2, a data-center-class RISC-V processor that shipped in 2025 — worth being precise that this is a CPU competing with x86 and Arm, not an AI accelerator (RISC-V International). The third front is hyperscaler silicon: Meta's MTIA inference accelerator uses RISC-V control and vector cores (Meta AI blog), and a RISC-V-based training chip has been reported in testing (Tom's Hardware), with the "still in testing" tag firmly attached.

Chips alone won't breach it

Here Part 1's conclusion trips things up again. The heart of Nvidia's moat lay in twenty years of accumulated software more than in the hardware. Open the chip with a free ISA, and the moat holds unless there are libraries, compilers, and developers to run on it. So the real front line sits next to the hardware, in software.

The most fundamental weapon on that front is OpenAI's Triton. Triton lets developers write GPU kernels in Python-like syntax, with the explicit goal of not being tied to any one vendor's hardware. Rebuilt on the MLIR compiler infrastructure since 2022, it lowers the same code to both Nvidia's PTX and AMD's AMDGCN (OpenAI and Red Hat). PyTorch's torch.compile uses Triton as a shared building block to generate code for Nvidia, AMD, and Intel backends, pulling framework-level dependence away from CUDA directly (PyTorch official).

AMD is going head-to-head with its own open stack, ROCm. Released in September 2025, ROCm 7.0 delivers up to 4x faster inference and 3x faster training than the previous ROCm 6, by the company's own account (AMD blog, 2025). Worth underlining: those multiples are AMD comparing itself to ROCm 6, not to CUDA. Paired with the MI350 series and its 288GB of HBM3e, it marks a shift "from research project to production platform."

Standards consortia have piled in as well. The Linux Foundation's UXL Foundation is building on Intel's oneAPI and SYCL as open standards to challenge CUDA, complete with SYCLomatic, a tool that ports CUDA code to SYCL. Its members include Arm, Fujitsu, Google Cloud, Intel, Qualcomm, and Samsung (The Register and SiliconANGLE, 2024). Then capital arrived. In June 2026, Qualcomm announced it would acquire Modular, a vendor-neutral inference stack, in an all-stock deal worth roughly $4 billion (multiple reports, June 2026). Led by Chris Lattner, the creator of LLVM and Swift, Modular is built around the Mojo language and the MAX runtime. The deal is still at the announcement stage, pending regulatory approval, with completion expected in the second half of 2026. Lattner has pledged that even after the acquisition, Modular won't stray from its mission of supporting every vendor's hardware (as reported by NAND Research and others).

For US readers, the stakes reach past the industry. The Center for Strategic and International Studies has argued that Washington "cannot disengage" from RISC-V, framing standards leadership itself as a security question (CSIS).

Open doesn't guarantee a win

The list of counterattacks runs long. But the story where open equals victory is premature. The counterevidence is already in.

The clearest case is Esperanto Technologies. Founded in 2014 around low-power RISC-V AI silicon, it delivered chip samples in 2021 and reached production in 2023 — then wound down its silicon business in July 2025. It cut headcount by 90%, and its IP passed to Nekko.ai (EE Times and XPU.pub, 2025). Low power, its point of difference, didn't sell in the market. Proof that the open camp fails too.

The maturity gap deserves a clear-eyed look. The RISC-V AI ecosystem is still early. The heavily optimized kernel libraries, the deep bench of developers, the sprawling documentation and community that CUDA has: those are all still thin, and that's usually where the real-world barriers appear (design-reuse and others). Fragmentation hasn't fully gone away either. RISC-V's modular design invites a proliferation of custom extensions, and that immaturity has pushed users back toward Arm and x86. RVA23 pressed hard on the problem without closing it out.

Even ROCm, the flagship of the open stacks, leaves a measurable gap in practice. On MFU, the metric for how efficiently a chip actually gets used, analysts estimate AMD at around 45% against Nvidia's 50-55%. Open, in other words, doesn't automatically deliver performance or maturity.

And the irony from the opening cuts both ways. Nvidia's heavy use of RISC-V, plus its plan to port CUDA on top of it, reads as a symbolic win for the open camp. It also reads as Nvidia pulling even the open standard into its own ecosystem, extending the life of its lock-in. The same fact serves as evidence of a win and a signal of absorption.

The series ahead

Two facts stand out from Part 2. The open-standard counterattack has moved past the paper stage into real silicon and real capital. And its success rides on how fast the software stack matures, not on the chip, which is why no one can yet call the ending.

One thread remains. One group has embraced open standards more urgently than any startup or hyperscaler: a nation-state. A royalty-free standard that sits outside the reach of export controls is an attractive card for a China looking to sidestep sanctions. It's why Alibaba has shipped server-grade RISC-V chips and Beijing is drafting incentives ministry by ministry. Part 3 digs into China's RISC-V localization strategy. The stretch where regulation moves market share directly was already covered in the export-controls installment.

One thing is clear. The attempt to pry the moat open has reached the hardware stage, and even its owner is riding the open standard now. But opening a road doesn't put cars on it. Who finishes the software to run there first: that's the next scene in this war.